ea72d66b6d
* Simplify verilator linter using ale command format strings * Verilator Linter: Restructure linter command tests * Verilator Linter: adds to the handler test the returned filename * Verilator Linter: add the current file path to the search path * Verilator Linter: Add the search path to the tests Co-authored-by: TG <tarik.graba@telecom-paris.fr>
52 lines
1.4 KiB
Text
52 lines
1.4 KiB
Text
Before:
|
|
runtime ale_linters/verilog/verilator.vim
|
|
|
|
After:
|
|
call ale#linter#Reset()
|
|
|
|
|
|
Execute (The verilator handler should parse legacy messages with only line numbers):
|
|
AssertEqual
|
|
\ [
|
|
\ {
|
|
\ 'lnum': 3,
|
|
\ 'type': 'E',
|
|
\ 'text': 'syntax error, unexpected IDENTIFIER',
|
|
\ 'filename': 'foo.v'
|
|
\ },
|
|
\ {
|
|
\ 'lnum': 10,
|
|
\ 'type': 'W',
|
|
\ 'text': 'Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).',
|
|
\ 'filename': 'bar.v'
|
|
\ },
|
|
\ ],
|
|
\ ale_linters#verilog#verilator#Handle(bufnr(''), [
|
|
\ '%Error: foo.v:3: syntax error, unexpected IDENTIFIER',
|
|
\ '%Warning-BLKSEQ: bar.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).',
|
|
\ ])
|
|
|
|
|
|
Execute (The verilator handler should parse new format messages with line and column numbers):
|
|
AssertEqual
|
|
\ [
|
|
\ {
|
|
\ 'lnum': 3,
|
|
\ 'col' : 1,
|
|
\ 'type': 'E',
|
|
\ 'text': 'syntax error, unexpected endmodule, expecting ;',
|
|
\ 'filename': 'bar.v'
|
|
\ },
|
|
\ {
|
|
\ 'lnum': 4,
|
|
\ 'col' : 6,
|
|
\ 'type': 'W',
|
|
\ 'text': 'Signal is not used: r',
|
|
\ 'filename': 'foo.v'
|
|
\ },
|
|
\ ],
|
|
\ ale_linters#verilog#verilator#Handle(bufnr(''), [
|
|
\ '%Error: bar.v:3:1: syntax error, unexpected endmodule, expecting ;',
|
|
\ '%Warning-UNUSED: foo.v:4:6: Signal is not used: r',
|
|
\ ])
|
|
|